连战马英九等五任国民党主席聚首 共商党产危机

Involves collaboration with Purdue and VLSI Startup. The project has several components: Application specific optimization of deep learning models for ASIC mapping, Circuit and Architecture design for in-memory computing based on SRAM and RRAM in advanced nodes, NOC modelling and evaluation for multi-core in memory computing architectures, spiking neural network scheme etc.

This project involves collaboration with VLSI firms and mixed signal IC design at advanced nodes.

Working on low power mixed signal ASICs for biomedical applications: involves a mix of analog, digital design and signal processing

RHBD implementation for a 10 bit, 100MSPS, pipelined ADC ( An ISRO Project)

Energy-efficiency and performance of on-chip global interconnects can be a major bottleneck for emerging chip-multi-processors (CMP) that employ extensive inter-processor and memory to processor communication. We explore the application of low-voltage, low-resistance spin-torque switches as compact and energy efficient trans-impedance amplifiers and can facilitate the design of ultra-low energy (0.1fJ/mm/Gbps, up to ~100x lower than CMOS interconnects) and compact I/O interfaces for global… Show more

Energy-efficiency and performance of on-chip global interconnects can be a major bottleneck for emerging chip-multi-processors (CMP) that employ extensive inter-processor and memory to processor communication. We explore the application of low-voltage, low-resistance spin-torque switches as compact and energy efficient trans-impedance amplifiers and can facilitate the design of ultra-low energy (0.1fJ/mm/Gbps, up to ~100x lower than CMOS interconnects) and compact I/O interfaces for global on-chip and inter-chip current-mode interconnects. Show less

The related projects target to develop low power and high performance information processing ASICs for a range of applications, like implantable bioelectronics, Ultra low power sensor nodes, Bio-sensor-CMOS interface etc. The work will include design optimization of DSP hardware along with the design of analog/RF CMOS front-end.

This project aims to develop photonic qubits with CMOS interface for control and readout

Exploring novel device-circuit designs for Magnetic Random Access Memory (MRAM) bit-cells for lower write-energy, improved speed, reliability and density. Novel sensing schemes for high-speed and low-energy sensing schemes for resistive memory and associated device-circuit design is being explored. The proposed sensing techniques can be ~4x faster and 90% more energy efficient as compared to conventional current-sensing schemes

Design of SET immune high-speed backplane I/O circuits for space applications (An ISRO project)

Radiation effects in outer space may lead to unwanted transient and long-duration disruption in circuit operations. Sponsored by ISRO, this project involves circuit design approaches for mixed signal blocks
that make them resistant towards such disruptions by suppressing the effects of spurious transients caused by such strikes.

Proposed novel device structure and solution to electrical coupling circuitry for designing low power and robust associative modules. Performed noise and variation analysis for the proposed scheme to verify design-feasibility and robustness. The on going work on this topic includes the design and fabrication of low power mixed-signal interface for the spintronic oscillators in 45nm CMOS technology, along with architecture-level optimizations. This project also involves design and tapeout of… Show more

Proposed novel device structure and solution to electrical coupling circuitry for designing low power and robust associative modules. Performed noise and variation analysis for the proposed scheme to verify design-feasibility and robustness. The on going work on this topic includes the design and fabrication of low power mixed-signal interface for the spintronic oscillators in 45nm CMOS technology, along with architecture-level optimizations. This project also involves design and tapeout of ‘approximate digital neural network’ as a bench-mark CMOS desgn. Show less